A phase locked loop (PLL) may be employed to clean up phase noise in a reference clock. The voltage controlled oscillator (VCO) for the PLL may be implemented as a ring oscillator formed of several delay cells arranged in series as a ring. Bias signals for the delay cells may be generated by an additional cell that is a replica of the delay cells.
In some applications, the output of the ring oscillator may be coupled to current-mode logic (CML). CML may be preferable to CMOS logic for some applications, because CML operates with differential signaling with a much smaller signal swing than CMOS logic, and therefore may be able to operate at higher speed than CMOS logic. However, the output common mode level of the ring oscillator may not be known or fixed, so that the coupling of the ring oscillator to the CML may present difficulties.